The present invention relates to a logic circuit and more particularly to an E/D logic circuit constituted by a depletion mode field-effect transistor (referred to as "D-mode FET" hereinafter) and an enhancement mode field-effect transistor (referred to as "E-mode FET" hereinafter).
Recently, an E/D logic circuit, e.g., an E/D inverter employing a D-mode FET as a load transistor and an E-mode FET as an input transistor has widely been used as a logic circuit integrated in a semiconductor integrated circuit, since such an E/D logic circuit has the following advantages. First, a D-mode FET, acting as a load transistor and having at one input a power supply voltage, can produce the power supply voltage at an output terminal without signal level reduction. Second, the D-mode FET operates as a constant current source and, hence, a load capacitance to be driven can be charged at a high speed. In such an E/D logic circuit, however, at least one input transistor is made conductive, and via this conducting transistor, a current flows through a D-mode FET as a load. The power consumption by this current naturally generates heat, resulting in a rise in temperature of the semiconductor chip, which makes the circuit operation conditions unstable and hinders logic circuits from being arranged with a high density.
Accordingly, if it is contrived to decrease the current flowing through the load transistor for reducing the power consumption, then the operating speed of the circuit lowers since it becomes impossible to charge at high speed the capacitance loaded onto the output terminal. In consequence, the conventional E/D logic circuit has a large power consumption as well as a limited operating speed. Therefore, it has been difficult to realize a large-scale integration thereof on a semiconductor chip.
The conventional semiconductor integrated circuit has a power consumption of not greater than about 1 watt in the case where the integration scale is smaller than 2000 gates and can be put into practical use by considering the heat dissipation of the chip. However, when integration scale of the integrated circuit is 10000 gates or more, the power consumption thereof becomes more than 5 watts, so that the circuit is no more practical.
Moreover, the operating speed of the conventional E/D logic circuit is unsatisfactory under the above-mentioned limitation of suppressing the power consumption. Particularly, the total operating speed has been obliged to be unsatisfactory in the circuit formed by cascading logic circuits over a multiplicity of stages.